The present invention relates to a wafer level package, and more particularly, to a wafer level package which is configured to compensate for a difference in size between a wafer level package and an FBGA (fine-pitch ball grid array) package.
In general, a package is manufactured by cutting a wafer into individual semiconductor chips and conducting a packaging process for each semiconductor chip. However, the packaging process includes by itself a number of unit processes such as die attaching, wire bonding, molding, trimming, forming, and so forth. Thus, in a conventional package manufacturing method in which the packaging process should be conducted for every semiconductor chip, a problem occurs in that, when considering the number of semiconductor chips obtained from one wafer, a time required for packaging all the semiconductor chips is too long.
In order to cope with this problem, recently, a method has been disclosed in the art, in which a packaging process is first conducted in the state of a wafer and the wafer is cut into individual packages to form a plurality of packages. A package manufactured in this way is called a wafer level package.
In the wafer level package, the re-distribution of pads through a re-distribution process must be necessarily performed, and therefore, the insertion of a buffer layer for alleviating a stress must be necessarily implemented.
Nevertheless, while the wafer level package has advantages in terms of processes, it has disadvantages as described below, so it is difficult to manufacture a wafer level package.
First, while not illustrated and explained, a wafer level package has solder balls as a mounting means to an outside circuit as in the case of an existing FBGA package. Therefore, since the wafer level package has a ball layout, when subsequently conducting a module process and a test process for the wafer level package, the infra of the existing FBGA package, that is, facilities and techniques which are employed in the module process and the test process for the FBGA package, must be employed as they are. In this regard, since the wafer level package is a different size from the FBGA package, the various techniques for the FBGA package cannot be employed as they are. Accordingly, an extended period is required and there are difficulties to mount and test the wafer level package.
Further, in the wafer level package, while the front surface of the semiconductor chip is covered by an insulation layer, the rear surface of the semiconductor chip is exposed to the outside. Hence, since the wafer level package has a structural limit in that the rear surface of the semiconductor chip is exposed to the outside, the wafer level package is weak to an external shock.
Moreover, as electronic or electric appliances trend toward miniaturization and slimness, the size of a package has decreased. In this regard, as the size of the wafer level package has decreased, the heat dissipation capability thereof has deteriorated, and as a result, the wafer level package has a poor thermal characteristic.